India’s Next-Generation Open RISC-V Compute Architecture.
SOKB Semiconductor™ (SOKB Pvt Ltd) is a deep-tech startup dealing in high-performance, production-grade digital IP blocks architected for sovereign compute autonomy. Aligned with the India Semiconductor Mission.
Direct integration with SCL Mohali test structures, Synopsys/Cadence toolchains via ChipIN, and generic SystemVerilog RTL verified on FPGA twins.
The Frontier is Moving. Introducing ATLAS-I.
The traditional boundaries of silicon are officially history. SOKB Semiconductor unveils a fundamental leap in hardware engineering: the ATLAS-I Chiplet Architecture. Built from the ground up for intense edge computing workloads, ATLAS-I delivers raw processing power without any thermal penalty.
Zero Thermal Throttle Leaks
Custom on-die power delivery layers curb extreme thermal leaks, maximizing operational clock limits without driving up power consumption.
Neural Network Matrix Acceleration
Packed physical matrix scaling layout designed intentionally to process extensive neural network calculations smoothly on edge devices.
Sovereign Concurrency Engine
Engineered to handle dense concurrent processing requests under high systemic strain with strict uptime and sovereign ownership guarantees.
Synchronization with India Semiconductor Mission (ISM 2.0)
Semicon 2.0 & DLI Deployment
SOKB Semiconductor directly leverages the upgraded Design Linked Incentive (DLI) scheme under MeitY, unlocking 50% design subsidy reimbursement across EDA software subscriptions, multi-project wafer (MPW) runs, and post-silicon ATMP operations.
Uttar Pradesh Semiconductor Hub
Strategically anchored in the Lucknow–Barabanki growth corridor of Uttar Pradesh, establishing an indigenous silicon VLSI layout and tape-out sign-off epicenter within North India's emerging semiconductor and defense industrial corridor.
Sovereign IP Ownership
100% Indian-controlled equity maintaining deep-tech startup criteria. All macro blocks and microarchitectural extensions are fully licensed by SOKB Pvt. Ltd. for ensuring sovereign autonomy.
SOKB Silicon IP Portfolio Matrix
TECHNOLOGY NODE: 40nm CMOS BULK • VERIFIED VIA SYSTEMVERILOG
Dual-Core ATLNode Processor Matrix
Engineered based on the proven ATLNode 3-stage pipelined architecture. Implements standard integer multiplication/division (M), atomic primitives (A), and compressed instructions (C) along with address calculation and bit manipulation acceleration (Zba/Zbb/Zbs). Optimized for 150-200 MHz on 40nm standard cell libraries.
64-Bit Multi-Master AXI4 Crossbar Interconnect
Full non-blocking high-bandwidth AXI4 matrix crossbar allowing simultaneous concurrent transactions between Core 0, Core 1, and the multi-channel DMA controller toward independent SRAM banks and peripheral bridges. Features parameterized FIFO queues, round-robin arbitration, and deadlock-free priority routing.
Unified 512 KB Synchronous SRAM & L1 Caches
High-density, low-leakage 40nm SRAM macro layout configured in four 128 KB dual-ported memory banks. Each ATLNode core integrates private 8 KB 2-way set-associative instruction cache and 8 KB write-through data cache to minimize interconnect contention during compute-intensive digital signal processing loops.
High-Speed Serial Host Interfaces & COTS Bridges
Dedicated asynchronous host macro blocks enabling high-throughput peripheral coupling without clock drift. Features a 100 MHz SDIO 3.0 interface for high-density storage/eMMC and custom high-speed SPI host bridges optimized for hosting commercial Wi-Fi/BLE/Sub-GHz transceivers on external companion modules.
Execution Metric Matrix: Option B (Digital Silicon) vs. Integrated RF
Why SOKB Semiconductor chose a 100% digital silicon tape-out trajectory to guarantee first-pass silicon yield under ISM DLI guidelines rather than single-die mixed-signal RF traps.
| Evaluation Vector | SOKB Option B (100% Digital Silicon + COTS Bridge) | Single-Die Integrated RF SoC (Option A Route) |
|---|---|---|
| Tape-Out Mask Set Complexity | Standard 40nm Digital CMOS (28-32 Mask Layers) | High-Cost Mixed-Signal RF CMOS (42-48 Mask Layers with Thick Metal & Deep N-Well) |
| First-Pass Silicon Yield Probability | > 92% (Deterministic Standard Cell Timing Closure) | < 58% (Susceptible to Substrate Noise & VCO Jitter) |
| EDA Tooling & Simulation Cycle | Fully covered via ChipIN Centre Digital Tooling (Design Compiler, Innovus, PrimeTime) | Requires specialized RF Spectre-RF, GoldenGate, & 3D EM extraction licenses (Extreme Cost) |
| Foundry Portability | High: Generic Verilog/SystemVerilog RTL ports across TSMC, GlobalFoundries, or SCL Mohali | Locked to single foundry RF-PDK (Requires multi-crore redesign if foundry shuttle cancels) |
| Regulatory & Wireless Certification | Fast-track: Pre-certified COTS modules (WPC/FCC/CE) eliminate costly anechoic chamber recertification | Requires 9-14 months of physical RF tuning, matching networks, and full WPC emissions compliance |
| Capital Efficiency & Fiscal Leverage | Maximum Fiscal Leverage: 100% digital flow backed by MeitY DLI match with zero wasted mask iterations | High CapEx Exposure: Complex RF re-spins with substantial non-subsidized foreign foundry overheads |
Partner with India's Sovereign RISC-V Compute Pioneer
SOKB Semiconductor is accepting engagement requests from Tier-1 hardware vendors, smart-metering original equipment manufacturers, and defense research organizations seeking silicon-proven sovereign IP.