ISM DLI Compliance & The Tape-Out Roadmap
Execution synchronization with the India Semiconductor Mission (ISM 2.0) Design Linked Incentive (DLI) framework, multi-project wafer (MPW) scheduling, and statutory DPIIT deep-tech governance.
Phase 1 to Phase 3 Execution Timeline (Months 1–24)
FPGA Emulation, ChipIN EDA Setup & COTS Hardware Twin
Synthesis and bring-up of the Dual-Core Hazard3 (RV32IMAC) processor matrix and 64-bit AXI4 crossbar on Xilinx Kintex-7/Zynq UltraScale+ FPGA platforms. Provisioning of enterprise EDA cloud instances via the MeitY-funded ChipIN Centre (Synopsys Design Compiler, PrimeTime, Cadence Innovus). Physical verification of asynchronous SPI host bridges connected to commercial off-the-shelf (COTS) Wi-Fi and Bluetooth companion radios, ensuring compatibility with SCL Mohali test structure baselines.
DLI Detailed Project Report (DPR) Clearance & Physical Design Sign-off
Formal Detailed Project Report (DPR) clearance through the dedicated Chips-DLI Portal under MeitY guidelines. Mobilization of the 50% design subsidy reimbursement tranche. Execution of full place-and-route (P&R), automated clock tree synthesis (CTS), power grid analysis, and sign-off Static Timing Analysis (STA) across all operating corners (SS/FF/TT) utilizing target 40nm standard cell libraries and PDKs.
GDSII Tape-Out, Multi-Project Wafer (MPW) Shuttle & ATMP Packaging
Final GDSII database lock and submission to tier-1 global pure-play foundry Multi-Project Wafer (MPW) shuttle (TSMC / GlobalFoundries / UMC 40nm node). Wafer dicing and post-silicon assembly, packaging into standard 64-pin QFN/BGA packages, and automated test equipment (ATE) functional characterization at accredited Indian packaging and testing (ATMP) facilities.
Sovereign Compliance Status Monitor
Rigorous tracking of SOKB Semiconductor's alignment with DPIIT deep-tech startup directives, domestic ownership mandates, and open-source intellectual property hygiene.
DPIIT Deep-Tech Startup Criteria
Formally structured under Startup India DPIIT recognition guidelines for semiconductor design and hardware IP creation. Meets the mandated R&D expenditure threshold (>15% of annual operational expenditure allocated strictly to core electronic VLSI engineering).
Domestic Equity Ownership Control
Complies strictly with the statutory DLI prerequisite of retaining greater than 50% equity shareholding by Indian resident citizens and promoters. Board voting control and management control remain exclusively domestic without foreign controlling covenants.
Open-Source Licensing Governance
Full legal audit completed for open RISC-V components (Hazard3 core licensed under permissive Apache 2.0). All proprietary peripheral macros and AXI4 crossbar IP maintain clear separation boundaries, protecting downstream commercial licensees from AGPL viral copyleft claims.
Complete documentation packs (Articles of Association, DPIIT Registration Certificate, Cap Table, and SystemVerilog Verification Reports) are available to ISM PMAC evaluators upon request.